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![Code Code](/uploads/1/1/9/0/119007815/664543420.jpg)
Exp-4 simulation of vhdl code for demultiplexer August 15, 2018 VLSI LAB DECE 2018 AIM: To design and develop an 1:8 output demultiplexer using VHDL code and simulate it.
Logic gate for an 8 to 4 Multiplexer (8to4MUX):- Design of 1: 4 Demultiplexer using with-select Concurrent Statement (VHDL Code). 09:17 naresh.dobal 1 comment Email This BlogThis!
- In this lecture we will learn about demultiplexer and its vhdl code.we will simulate demultiplexer using EDA Playground.
It has 3 inputs: 1-bit sel (selector), 4-bit X[3.0] and 4-bit Y[3.0]. It uses two 4to2 Multiplexer blocks (4to2MUX). It has one 4-bit output m[3.0].
![Vhdl Code For Demux 1 To 4 Vhdl Code For Demux 1 To 4](/uploads/1/1/9/0/119007815/979343523.jpg)
Vhdl Code For Demux 1 To 40
Vhdl Code For Demux 1 To 42
-- 8 to 4 Multiplexer
-- inputs: 1-bit sel (selector), 4-bit X, 4-bit Y
-- outputs: 4-bit m
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity MUX8_4 is
PORT( sel: in bit;
X, Y: in bit_vector(3 downto 0);
m: out bit_vector(3 downto 0));
end MUX8_4;
architecture logic of MUX8_4 is
component MUX4_2 is
PORT( sel, X0, X1, Y0, Y1: in bit;
m0, m1: out bit);
end component;
begin
mux4_2_inst0 : MUX4_2
PORT MAP( sel => sel, X0 => X(0), X1 => X(1), Y0 => Y(0), Y1 => Y(1),
m0 => m(0), m1 => m(1));
mux4_2_inst1 : MUX4_2
PORT MAP( sel => sel, X0 => X(2), X1 => X(3), Y0 => Y(2), Y1 => Y(3),
m0 => m(2), m1 => m(3));
end logic;
-- inputs: 1-bit sel (selector), 4-bit X, 4-bit Y
-- outputs: 4-bit m
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity MUX8_4 is
PORT( sel: in bit;
X, Y: in bit_vector(3 downto 0);
m: out bit_vector(3 downto 0));
end MUX8_4;
architecture logic of MUX8_4 is
component MUX4_2 is
PORT( sel, X0, X1, Y0, Y1: in bit;
m0, m1: out bit);
end component;
begin
mux4_2_inst0 : MUX4_2
PORT MAP( sel => sel, X0 => X(0), X1 => X(1), Y0 => Y(0), Y1 => Y(1),
m0 => m(0), m1 => m(1));
mux4_2_inst1 : MUX4_2
PORT MAP( sel => sel, X0 => X(2), X1 => X(3), Y0 => Y(2), Y1 => Y(3),
m0 => m(2), m1 => m(3));
end logic;